extends verilog
extends fpga
extends simulation
extends interface

snippet always_ff "sequential logic"
always_ff @ (posedge ${1:clk})
begin
    ${3:/*code*/}
end
endsnippet

snippet always_comb "combination logic"
always_comb
begin
    ${1:/*code*/}
end
endsnippet

snippet always_latch "D latch"
always_latch
begin
    ${1:/*code*/}
end
endsnippet

snippet log "logic"
logic                       ${1:inport};
endsnippet

snippet logw "logic  [xx:00]"
logic   [${1:MSB}:00]             ${2:inport};
endsnippet
# 
# snippet in "input logic  inport"
# input   logic               ${1:inport},
# endsnippet
# 
# snippet in "input wire [MSB:0] inport"
# input   logic   [${1:MSB}:00]     ${2:inport},
# endsnippet
# 
# #output
# snippet our "logic  xxx"
# output  logic               ${1:outport},
# endsnippet
# 
# snippet our    "logic  [MSB:00]"
# output  logic   [${1:MSB}:00]     ${2:outport},
# endsnippet

# snippet state   "one hot encode machine state"
# typedef enum logic [2:0] 
# {
#     IDLE    = 3'b001,
#     PROCESS = 3'b010,
#     OVER    = 3'b100
# } state_t;
# state_t cs = IDLE, ns = IDLE;
# logic   [15:00]         state_cnt = 0;
# logic   [15:00]         state_cnt_n = 0;
# 
# always_ff @(posedge clk)
# begin
#     cs <= ns;
# end
# 
# always_comb 
# begin
#     ns = cs;  // 默认保持当前状态
#     case (cs)
#     IDLE: 
#     begin
#     end
# 
#     default: ns = IDLE;
#     endcase
# end
# 
# always_ff @(posedge clk)
# begin
#     state_cnt <= state_cnt_n;
# end
# 
# always_comb 
# begin
#     if (cs != ns)
#         state_cnt_n = 0;
#     else
#         state_cnt_n = state_cnt + 1'b1;
# end
# 
# endsnippet

snippet tds  "typedef struct"
typedef struct packed
{
    /*data*/;
}${1:/*struct*/}_t;
endsnippet

snippet foreach
foreach(${1:name}[${2:index}])
endsnippet

snippet task    "systemverilog task template"
task ${1:name}($2);
    $3
endtask
endsnippet

snippet function     "systemverilog function template"
function ${1:void} ${2:name}($3);
$4
endfunction
endsnippet

snippet assert  "assert ... else"
assert(${1:condition})
else
    $error(${2:failed});
endsnippet

snippet urandom	"urandom_range"
${1:veriable} = \$urandom_range(0, 255);
endsnippet

snippet tde "typdef enum"
typedef enum logic[07:00]
{
    IDLE = 8'h01,
    WRITE
    //and so on
}${1:name}_e;
$1_e      /*instance*/;
endsnippet

snippet bit_stream_left "left-to-right streaming operator"
// data = 32'hAABBCCDD -->  result = {>>8{data}};  --> result = 32'hDDCC_BBAA
// data = 32'hAABBCCDD -->  result = {>>16{data}}; --> result = 32'hCCDD_AABB
${1:dest} = {>>${2:width}{${3:source}}};
endsnippet

snippet bit_stream_right "right to left streaming operator"

// width=8时，两种操作结果一致
// data = 32'hAABBCCDD -->  result = {<<16{data}}; --> result = 32'hBBAA_DDCC
${1:dest} = {<<${2:width}{${3:source}}};
endsnippet
